Memory Cell

The circuit below is out of date:

I'm aiming for about eight registers at 16 bits each and I'm expecting the transistors used in these to be the majority of the total transistor count, that means that the memory cell design is critical for determining the transistor count.   The transistor count is both important in terms of cost but also ease of construction, portability, etc.

It's an absolute requirement that the workings of the processor are visible, so that means driving an LED so that the state of every bit can be seen.   This rules out any capacitor driven DRAM (large capacitors are too expensive).

The fundamental design is based on the flip-flop.   The hardest part is writing data, so let's start with that.   The flip-flop has a state, Si, there is data in to be written, IN, there is a write enable signal and there is an output state, So.   If WE is low then So = Si and if WE is high then So = IN.  Logically:


NOT WE can be generated for all memory cells.   AND and OR can be implemented with diodes to give this memory cell architecture (which includes the read logic):

The left hand side does the write, the right hand side does the read (to two buses).  Let's say we want to write, then we set WE high and the left AND circuit has the value of IN, where as the next AND circuit is low (as !WE is low).   The OR of these two AND circuits is therefore the value of IN.  Hence the base of NPN1 is set to IN, if it's high then the transistor conducts and the LED light is lit.   R3 sends a low to NPN2 which is then off.   When WE is low, !WE is high, so the output of NPN2 is fed back into NPN1 and a bit is stored.

The right hand side does the read and is considerably easier.  Both OUT0 and OUT1 are AND functions of the relevant read enable signal (RE0 and RE1 respectively).


Or maybe it's not.  Standard DRAM one capacitor one transistor per bit would be great, but it wouldn't allow for a LED to show the state.